mirror of
https://github.com/rizonesoft/Notepad3.git
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+upd: VHDL Lexer
This commit is contained in:
METANEOCORTEX\Kotti
parent
1e89129af8
commit
598c168589
@ -235,8 +235,9 @@ static void FoldNoBoxVHDLDoc(
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// Decided it would be smarter to have the lexer have all keywords included. Therefore I
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// don't check if the style for the keywords that I use to adjust the levels.
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char words[] =
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"architecture begin block case component else elsif end entity for generate loop package process record then "
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"procedure protected function when units";
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"architecture begin block case component configuration context else elsif end entity for function "
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"generate if loop package procedure process protected record then units view when";
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WordList keywords;
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keywords.Set(words);
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@ -2,47 +2,111 @@
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// ----------------------------------------------------------------------------
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KEYWORDLIST KeyWords_VHDL =
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{
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"access after alias all architecture array assert attribute begin block body buffer bus case component "
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"configuration constant disconnect downto else elsif end entity exit file for function generate generic "
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static KEYWORDLIST KeyWords_VHDL = {
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// 0 Keywords
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"access after alias all architecture array assert assume assume_guarantee attribute begin block body buffer bus case component "
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"configuration constant context cover default disconnect downto else elsif end entity exit fairness file for force function generate generic "
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"group guarded if impure in inertial inout is label library linkage literal loop map new next null of on "
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"open others out package port postponed procedure process pure range record register reject report return "
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"select severity shared signal subtype then to transport type unaffected units until use variable wait "
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"open others out package parameter port postponed private procedure process property protect protected pure "
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"range record register reject release report restrict restrict_guarantee return "
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"select sequence severity shared signal strong subtype then to transport type unaffected units until use variable view vmode vpkg vprop vunit wait "
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"when while with",
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// 1 Operators
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"abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor",
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"active ascending base delayed driving driving_value endfile event falling_edge high image instance_name, "
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"is_x last_active last_event last_value left leftof length low now path_name pos pred quiet range read "
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"readline resize resolved reverse_range right rightof rising_edge rotate_left rotate_right shift_left "
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"shift_right simple_name stable std_match succ to_01 to_UX01 to_bit to_bitvector to_integer to_signed "
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// 2 Attributes
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"active ascending base converse delayed designated_subtype driving driving_value endfile element event falling_edge foreign high image index instance_name, "
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"is_x last_active last_event last_value left leftof length low now path_name pos pred quiet range read record "
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"readline reflect resize resolved reverse_range right rightof rising_edge rotate_left rotate_right shift_left "
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"shift_right signal simple_name stable std_match subtype succ to_01 to_UX01 to_bit to_bitvector to_integer to_signed "
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"to_stdlogicvector to_stdulogic to_stdulogicvector to_unsigned to_x01 to_x01z transaction val value "
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"write writeline",
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"ieee math_complex math_real numeric_bit numeric_std standard std std_logic_1164 std_logic_arith "
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"std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned textio vital_primitives "
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"vital_timing work",
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"UX01 UX01Z X01 X01Z bit bit_vector boolean character delay_length file_open_kind file_open_status integer "
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"line natural positive real severity_level side signed std_logic std_logic_vector std_ulogic "
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"std_ulogic_vector string text time unsigned width",
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// 3 Functions
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"add add_carry arccos arccosh arcsin arcsinh arctan arctanh arg "
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"binary_read binary_write bitstoreal bread break_number bwrite "
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"cbrt ceil classfp cmplx complex_to_polar conj copysign cos cosh "
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"deallocate dir_close dir_createdir dir_deletedir dir_deletefile dir_itemexists dir_itemisdir dir_itemisfile "
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"dir_open dir_workingdir divide dividebyp2 "
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"endfile epoch epoch eq exp "
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"falling_edge file_close file_line file_mode file_name file_open file_path file_rewind file_seek file_size "
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"file_tell file_truncate find_leftmost find_rightmost finish finish finite floor flush "
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"from_binary_string from_bstring from_hex_string from_hstring from_octal_string from_ostring from_string "
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"ge get_call_path get_principal_value getenv gmtime gmtime gt hex_read hex_write hread hwrite "
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"is_negative is_x isnan justify le localtime localtime log log10 log2 logb lt "
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"mac maximum minimum modulo multiply nanfp ne neg_inffp neg_zerofp nextafter normalize now "
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"octal_read octal_write oread owrite polar_to_complex pos_inffp qnanfp "
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"read readline realmax realmin realtobits reciprocal remainder resize resolution_limit resolved rising_edge "
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"rotate_left rotate_right round "
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"saturate scalb seconds_to_time sfix_high sfix_low sfixed_high sfixed_low shift_left shift_right "
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"sign sin sinh sqrt sread std_match stop stop string_read string_write subtract swrite "
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"tan tanh tee time_to_seconds to_01 to_binary_string to_bit to_bit_vector to_bitvector to_bstring to_bv "
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"to_float to_float128 to_float32 to_float64 to_hex_string to_hstring to_integer to_octal_string to_ostring "
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"to_real to_sfix to_sfixed to_signed to_slv "
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"to_std_logic_vector to_std_ulogic_vector to_stdlogicvector to_stdulogic to_stdulogicvector to_string to_sulv "
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"to_ufix to_ufixed to_unsigned to_ux01 to_x01 to_x01z tool_edition tool_name tool_type tool_vendor tool_version "
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"trunc "
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"ufix_high ufix_low ufixed_high ufixed_low uniform unordered vhdl_version write writeline zerofp",
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// 4 Packages
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"env fixed_float_types fixed_generic_pkg fixed_pkg float_generic_pkg float_pkg ieee math_complex math_real "
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"numeric_bit numeric_bit_unsigned numeric_std reflection standard std std_logic_1164 std_logic_arith std_logic_misc "
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"std_logic_signed, std_logic_textio std_logic_unsigned textio vital_primitives vital_timing work",
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// 5 Types
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"bit bit_vector boolean boolean_vector "
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"call_path_element call_path_vector call_path_vector_ptr character complex complex_polar "
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"dayofweek delay_length dir_create_status dir_delete_status dir_open_status direction directory directory_items "
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"file_delete_status file_open_kind file_open_state file_open_status file_origin_kind "
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"fixed_overflow_style_type fixed_round_style_type float float128 float32 float64 "
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"integer integer_vector line line_vector natural positive positive_real principal_value real real_vector round_type "
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"severity_level sfixed side signed std_logic std_logic_vector std_ulogic std_ulogic_vector string "
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"text time time_record time_vector "
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"u_float u_float128 u_float32 u_float64 u_sfixed u_signed u_ufixed u_unsigned ufixed "
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"unresolved_float unresolved_float128 unresolved_float32 unresolved_float64 unresolved_sfixed unresolved_signed "
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"unresolved_ufixed unresolved_unsigned unsigned ux01 ux01z "
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"valid_fpstate width x01 x01z",
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// 6 User (Constants)
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"append_mode ascending descending dir_separator error "
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"failure false "
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"file_origin_begin file_origin_current file_origin_end fixed_round fixed_saturate fixed_truncate fixed_wrap "
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"fphdlsynth_or_real friday "
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"input isx left left_index "
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"math_1_over_e math_1_over_pi math_1_over_sqrt_2 math_2_pi math_3_pi_over_2 math_cbase_1 math_cbase_j math_czero "
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"math_deg_to_rad math_e math_log10_of_e math_log2_of_e math_log_of_10 math_log_of_2 "
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"math_pi math_pi_over_2 math_pi_over_3 math_pi_over_4 math_rad_to_deg math_sqrt_2 math_sqrt_pi mode_error monday "
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"name_error nan neg_denormal neg_inf neg_normal neg_zero note open_ok output pos_denormal pos_inf pos_normal pos_zero "
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"quiet_nan read_mode read_write_mode resolved right right_index round_inf round_nearest round_neginf round_zero "
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"saturday state_closed state_open status_access_denied status_error status_item_exists "
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"status_no_directory status_no_file status_not_empty status_not_found status_ok sunday "
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"thursday true tuesday warning wednesday write_mode",
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NULL,
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};
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EDITLEXER lexVHDL =
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{
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SCLEX_VHDL, "vhdl", IDS_LEX_VHDL, L"VHDL", L"vhdl; vhd", L"",
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&KeyWords_VHDL, {
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{ {STYLE_DEFAULT}, IDS_LEX_STR_63126, L"Default", L"", L"" },
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//{ {SCE_VHDL_DEFAULT}, IDS_LEX_STR_63126, L"Default", L"", L"" },
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{ {MULTI_STYLE(SCE_VHDL_COMMENTLINEBANG, SCE_VHDL_COMMENT, SCE_VHDL_BLOCK_COMMENT, 0)}, IDS_LEX_STR_63127, L"Comment", L"fore:#008800", L"" },
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{ {MULTI_STYLE(SCE_VHDL_COMMENT, SCE_VHDL_COMMENTLINEBANG, SCE_VHDL_BLOCK_COMMENT, 0)}, IDS_LEX_STR_63127, L"Comment", L"fore:#008800", L"" },
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{ {SCE_VHDL_NUMBER}, IDS_LEX_STR_63130, L"Number", L"fore:#FF0000", L"" },
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{ {MULTI_STYLE(SCE_VHDL_STRING, SCE_VHDL_STRINGEOL, 0, 0)}, IDS_LEX_STR_63131, L"String", L"fore:#008000", L"" },
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{ {SCE_VHDL_OPERATOR}, IDS_LEX_STR_63132, L"Operator", L"fore:#B000B0", L"" },
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{ {SCE_VHDL_IDENTIFIER}, IDS_LEX_STR_63129, L"Identifier", L"", L"" },
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{ {SCE_VHDL_KEYWORD}, IDS_LEX_STR_63128, L"Keyword", L"bold; fore:#0A246A", L"" },
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{ {SCE_VHDL_KEYWORD}, IDS_LEX_STR_63128, L"Keyword", L"bold; fore:#0000FF", L"" },
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{ {SCE_VHDL_STDOPERATOR}, IDS_LEX_STR_63336, L"Standard Operator", L"bold; fore:#0A246A", L"" },
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{ {SCE_VHDL_ATTRIBUTE}, IDS_LEX_STR_63337, L"Attribute", L"", L"" },
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{ {SCE_VHDL_STDFUNCTION}, IDS_LEX_STR_63338, L"Standard Function", L"", L"" },
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{ {SCE_VHDL_STDPACKAGE}, IDS_LEX_STR_63339, L"Standard Package", L"", L"" },
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{ {SCE_VHDL_STDTYPE}, IDS_LEX_STR_63340, L"Standard Type", L"fore:#FF8000", L"" },
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{ {SCE_VHDL_USERWORD}, IDS_LEX_STR_63274, L"Constant", L"fore:#A400A4", L"" },
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EDITLEXER_SENTINEL
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}
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};
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@ -1 +1,243 @@
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The purpose of this dummy file is to create this directory.
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-- Simple Microprocessor Design (ESD Book Chapter 3)
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-- Copyright 2001 Weijun Zhang
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--
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-- DATAPATH composed of Multiplexor, Register File and ALU
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-- VHDL structural modeling
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-- datapath.vhd
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----------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity datapath is
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port( clock_dp: in std_logic;
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rst_dp: in std_logic;
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imm_data: in std_logic_vector(15 downto 0);
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mem_data: in std_logic_vector(15 downto 0);
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RFs_dp: in std_logic_vector(1 downto 0);
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RFwa_dp: in std_logic_vector(3 downto 0);
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RFr1a_dp: in std_logic_vector(3 downto 0);
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RFr2a_dp: in std_logic_vector(3 downto 0);
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RFwe_dp: in std_logic;
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RFr1e_dp: in std_logic;
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RFr2e_dp: in std_logic;
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jp_en: in std_logic;
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ALUs_dp: in std_logic_vector(1 downto 0);
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oe_dp: in std_logic;
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ALUz_dp: out std_logic;
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RF1out_dp: out std_logic_vector(15 downto 0);
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ALUout_dp: out std_logic_vector(15 downto 0);
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bufout_dp: out std_logic_vector(15 downto 0)
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);
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end datapath;
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architecture struct of datapath is
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component smallmux is
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port( I0: in std_logic_vector(15 downto 0);
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I1: in std_logic_vector(15 downto 0);
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I2: in std_logic_vector(15 downto 0);
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Sel: in std_logic_vector(1 downto 0);
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O: out std_logic_vector(15 downto 0)
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);
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end component;
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component reg_file is
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port ( clock : in std_logic;
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rst : in std_logic;
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RFwe : in std_logic;
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RFr1e : in std_logic;
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RFr2e : in std_logic;
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RFwa : in std_logic_vector(3 downto 0);
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RFr1a : in std_logic_vector(3 downto 0);
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RFr2a : in std_logic_vector(3 downto 0);
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RFw : in std_logic_vector(15 downto 0);
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RFr1 : out std_logic_vector(15 downto 0);
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RFr2 : out std_logic_vector(15 downto 0)
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);
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end component;
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component alu is
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port ( num_A: in std_logic_vector(15 downto 0);
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num_B: in std_logic_vector(15 downto 0);
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jpsign: in std_logic;
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ALUs: in std_logic_vector(1 downto 0);
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ALUz: out std_logic;
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ALUout: out std_logic_vector(15 downto 0)
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);
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end component;
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component obuf is
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port( O_en: in std_logic;
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obuf_in: in std_logic_vector(15 downto 0);
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obuf_out: out std_logic_vector(15 downto 0)
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);
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end component;
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signal mux2rf, rf2alu1: std_logic_vector(15 downto 0);
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signal rf2alu2, alu2memmux: std_logic_vector(15 downto 0);
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begin
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U1: smallmux port map(alu2memmux, mem_data,
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imm_data, RFs_dp, mux2rf);
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U2: reg_file port map(clock_dp, rst_dp, RFwe_dp,
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RFr1e_dp, RFr2e_dp,
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RFwa_dp, RFr1a_dp, RFr2a_dp,
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mux2rf, rf2alu1, rf2alu2 );
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U3: alu port map( rf2alu1, rf2alu2, jp_en, ALUs_dp,
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ALUz_dp, alu2memmux);
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U4: obuf port map(oe_dp, mem_data, bufout_dp);
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ALUout_dp <= alu2memmux;
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RF1out_dp <= rf2alu1;
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end struct;
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--------------------------------------------------------
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-- Simple Microprocessor Design
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--
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-- memory 256*16
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-- 8 bit address; 16 bit data
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-- memory.vhd
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--------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use work.constant_lib.all;
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entity memory is
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port ( clock : in std_logic;
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rst : in std_logic;
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Mre : in std_logic;
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Mwe : in std_logic;
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address : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(15 downto 0);
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data_out: out std_logic_vector(15 downto 0)
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);
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end memory;
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architecture behv of memory is
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type ram_type is array (0 to 255) of
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std_logic_vector(15 downto 0);
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signal tmp_ram: ram_type;
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begin
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write: process(clock, rst, Mre, address, data_in)
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begin
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if rst='1' then
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tmp_ram <= (------------------------------------------------------------
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-- following instruction for debugging purpose
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-- 0 => "0011001000101011", -- R2 <= #2B
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-- 1 => "0011001100001001", -- R3 <= #09
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-- 2 => "0001001100001010", -- M[A] <= R3
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-- 3 => "0000011000001000", -- R6 <= M[8]
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-- 4 => "0010001100100000", -- M[R3] <= R2
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-- 5 => "0100001100100000", -- R3 <= R3 + R2
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-- 6 => "0101001001100000", -- R2 <= R2 - R6
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-- 7 => "0110000000000000", -- jz if R0=0
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-- 8 => "1111000000000000", -- halt
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-------------------------------------------------------------
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-- program to generate 10 fabonacci number
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0 => "0011000000000000", -- mov R0, #0
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1 => "0011000100000001", -- mov R1, #1
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2 => "0011001000110100", -- mov R2, #52
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3 => "0011001100000001", -- mov R3, #1
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4 => "0001000000110010", -- mov M[50], R0
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5 => "0001000100110011", -- mov M[51], R1
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6 => "0001000101100100", -- mov M[100], R1
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7 => "0100000100000000", -- add R1, R0
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8 => "0000000001100100", -- mov M[100], R0
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9 => "0010001000010000", -- mov M[R2], R1
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10 => "0100001000110000", -- add R2, R3
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11 => "0000010000111011", -- mov R4, M[59]
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12 => "0110010000000101", -- jz R4, #6
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13 => "0111000000110010", -- output M[50]
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14 => "0111000000110011", -- ,, M[51]
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15 => "0111000000110100", -- ,, M[52]
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16 => "0111000000110101", -- ,, M[53]
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17 => "0111000000110110", -- ,, M[54]
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18 => "0111000000110111", -- ,, M[55]
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19 => "0111000000111000", -- ,, M[56]
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20 => "0111000000111001", -- ,, M[57]
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21 => "0111000000111010", -- ,, M[58]
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22 => "0111000000111011", -- ,, M[59]
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23 => "1111000000000000", -- halt
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others => "0000000000000000");
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else
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if (clock'event and clock = '1') then
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if (Mwe ='1' and Mre = '0') then
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tmp_ram(conv_integer(address)) <= data_in;
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end if;
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end if;
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end if;
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end process;
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read: process(clock, rst, Mwe, address)
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begin
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if rst='1' then
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data_out <= ZERO;
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else
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if (clock'event and clock = '1') then
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if (Mre ='1' and Mwe ='0') then
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data_out <= tmp_ram(conv_integer(address));
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end if;
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end if;
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end if;
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end process;
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end behv;
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--------------------------------------------------------
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-- Simple Microprocessor Design (ESD Book Chapter 3)
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-- Copyright 2001 Weijun Zhang
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--
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-- big multiplexor of control unit has
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-- four 16-bit inputs and one 16-bit output
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-- bigmux.vhd
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--------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity bigmux is
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port( Ia: in std_logic_vector(15 downto 0);
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Ib: in std_logic_vector(15 downto 0);
|
||||
Ic: in std_logic_vector(15 downto 0);
|
||||
Id: in std_logic_vector(15 downto 0);
|
||||
Option: in std_logic_vector(1 downto 0);
|
||||
Muxout: out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end bigmux;
|
||||
|
||||
architecture behv of bigmux is
|
||||
|
||||
begin
|
||||
|
||||
process(Ia, Ib, Ic, Id, Option)
|
||||
begin
|
||||
case Option is
|
||||
when "00" => Muxout <= Ia;
|
||||
when "01" => Muxout <= Ib;
|
||||
when "10" => Muxout <= Ic;
|
||||
when "11" => Muxout <= Id;
|
||||
when others =>
|
||||
end case;
|
||||
end process;
|
||||
|
||||
end behv;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user