From 598c1685893028b426ff4f0355434629f63fe1ca Mon Sep 17 00:00:00 2001 From: "METANEOCORTEX\\Kotti" Date: Sun, 19 Mar 2023 14:14:23 +0100 Subject: [PATCH] +upd: VHDL Lexer --- lexilla/lexers/LexVHDL.cxx | 5 +- src/StyleLexers/styleLexVHDL.c | 100 +++++-- .../StyleLexers/styleLexVHDL/Sample_VHDL.vhdl | 244 +++++++++++++++++- 3 files changed, 328 insertions(+), 21 deletions(-) diff --git a/lexilla/lexers/LexVHDL.cxx b/lexilla/lexers/LexVHDL.cxx index 008d34576..352925152 100644 --- a/lexilla/lexers/LexVHDL.cxx +++ b/lexilla/lexers/LexVHDL.cxx @@ -235,8 +235,9 @@ static void FoldNoBoxVHDLDoc( // Decided it would be smarter to have the lexer have all keywords included. Therefore I // don't check if the style for the keywords that I use to adjust the levels. char words[] = - "architecture begin block case component else elsif end entity for generate loop package process record then " - "procedure protected function when units"; + "architecture begin block case component configuration context else elsif end entity for function " + "generate if loop package procedure process protected record then units view when"; + WordList keywords; keywords.Set(words); diff --git a/src/StyleLexers/styleLexVHDL.c b/src/StyleLexers/styleLexVHDL.c index cb74d66b0..00182215b 100644 --- a/src/StyleLexers/styleLexVHDL.c +++ b/src/StyleLexers/styleLexVHDL.c @@ -2,47 +2,111 @@ // ---------------------------------------------------------------------------- -KEYWORDLIST KeyWords_VHDL = -{ - "access after alias all architecture array assert attribute begin block body buffer bus case component " - "configuration constant disconnect downto else elsif end entity exit file for function generate generic " +static KEYWORDLIST KeyWords_VHDL = { + + // 0 Keywords + "access after alias all architecture array assert assume assume_guarantee attribute begin block body buffer bus case component " + "configuration constant context cover default disconnect downto else elsif end entity exit fairness file for force function generate generic " "group guarded if impure in inertial inout is label library linkage literal loop map new next null of on " - "open others out package port postponed procedure process pure range record register reject report return " - "select severity shared signal subtype then to transport type unaffected units until use variable wait " + "open others out package parameter port postponed private procedure process property protect protected pure " + "range record register reject release report restrict restrict_guarantee return " + "select sequence severity shared signal strong subtype then to transport type unaffected units until use variable view vmode vpkg vprop vunit wait " "when while with", + + // 1 Operators "abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor", - "active ascending base delayed driving driving_value endfile event falling_edge high image instance_name, " - "is_x last_active last_event last_value left leftof length low now path_name pos pred quiet range read " - "readline resize resolved reverse_range right rightof rising_edge rotate_left rotate_right shift_left " - "shift_right simple_name stable std_match succ to_01 to_UX01 to_bit to_bitvector to_integer to_signed " + + // 2 Attributes + "active ascending base converse delayed designated_subtype driving driving_value endfile element event falling_edge foreign high image index instance_name, " + "is_x last_active last_event last_value left leftof length low now path_name pos pred quiet range read record " + "readline reflect resize resolved reverse_range right rightof rising_edge rotate_left rotate_right shift_left " + "shift_right signal simple_name stable std_match subtype succ to_01 to_UX01 to_bit to_bitvector to_integer to_signed " "to_stdlogicvector to_stdulogic to_stdulogicvector to_unsigned to_x01 to_x01z transaction val value " "write writeline", - "ieee math_complex math_real numeric_bit numeric_std standard std std_logic_1164 std_logic_arith " - "std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned textio vital_primitives " - "vital_timing work", - "UX01 UX01Z X01 X01Z bit bit_vector boolean character delay_length file_open_kind file_open_status integer " - "line natural positive real severity_level side signed std_logic std_logic_vector std_ulogic " - "std_ulogic_vector string text time unsigned width", + + // 3 Functions + "add add_carry arccos arccosh arcsin arcsinh arctan arctanh arg " + "binary_read binary_write bitstoreal bread break_number bwrite " + "cbrt ceil classfp cmplx complex_to_polar conj copysign cos cosh " + "deallocate dir_close dir_createdir dir_deletedir dir_deletefile dir_itemexists dir_itemisdir dir_itemisfile " + "dir_open dir_workingdir divide dividebyp2 " + "endfile epoch epoch eq exp " + "falling_edge file_close file_line file_mode file_name file_open file_path file_rewind file_seek file_size " + "file_tell file_truncate find_leftmost find_rightmost finish finish finite floor flush " + "from_binary_string from_bstring from_hex_string from_hstring from_octal_string from_ostring from_string " + "ge get_call_path get_principal_value getenv gmtime gmtime gt hex_read hex_write hread hwrite " + "is_negative is_x isnan justify le localtime localtime log log10 log2 logb lt " + "mac maximum minimum modulo multiply nanfp ne neg_inffp neg_zerofp nextafter normalize now " + "octal_read octal_write oread owrite polar_to_complex pos_inffp qnanfp " + "read readline realmax realmin realtobits reciprocal remainder resize resolution_limit resolved rising_edge " + "rotate_left rotate_right round " + "saturate scalb seconds_to_time sfix_high sfix_low sfixed_high sfixed_low shift_left shift_right " + "sign sin sinh sqrt sread std_match stop stop string_read string_write subtract swrite " + "tan tanh tee time_to_seconds to_01 to_binary_string to_bit to_bit_vector to_bitvector to_bstring to_bv " + "to_float to_float128 to_float32 to_float64 to_hex_string to_hstring to_integer to_octal_string to_ostring " + "to_real to_sfix to_sfixed to_signed to_slv " + "to_std_logic_vector to_std_ulogic_vector to_stdlogicvector to_stdulogic to_stdulogicvector to_string to_sulv " + "to_ufix to_ufixed to_unsigned to_ux01 to_x01 to_x01z tool_edition tool_name tool_type tool_vendor tool_version " + "trunc " + "ufix_high ufix_low ufixed_high ufixed_low uniform unordered vhdl_version write writeline zerofp", + + // 4 Packages + "env fixed_float_types fixed_generic_pkg fixed_pkg float_generic_pkg float_pkg ieee math_complex math_real " + "numeric_bit numeric_bit_unsigned numeric_std reflection standard std std_logic_1164 std_logic_arith std_logic_misc " + "std_logic_signed, std_logic_textio std_logic_unsigned textio vital_primitives vital_timing work", + + // 5 Types + "bit bit_vector boolean boolean_vector " + "call_path_element call_path_vector call_path_vector_ptr character complex complex_polar " + "dayofweek delay_length dir_create_status dir_delete_status dir_open_status direction directory directory_items " + "file_delete_status file_open_kind file_open_state file_open_status file_origin_kind " + "fixed_overflow_style_type fixed_round_style_type float float128 float32 float64 " + "integer integer_vector line line_vector natural positive positive_real principal_value real real_vector round_type " + "severity_level sfixed side signed std_logic std_logic_vector std_ulogic std_ulogic_vector string " + "text time time_record time_vector " + "u_float u_float128 u_float32 u_float64 u_sfixed u_signed u_ufixed u_unsigned ufixed " + "unresolved_float unresolved_float128 unresolved_float32 unresolved_float64 unresolved_sfixed unresolved_signed " + "unresolved_ufixed unresolved_unsigned unsigned ux01 ux01z " + "valid_fpstate width x01 x01z", + + // 6 User (Constants) + "append_mode ascending descending dir_separator error " + "failure false " + "file_origin_begin file_origin_current file_origin_end fixed_round fixed_saturate fixed_truncate fixed_wrap " + "fphdlsynth_or_real friday " + "input isx left left_index " + "math_1_over_e math_1_over_pi math_1_over_sqrt_2 math_2_pi math_3_pi_over_2 math_cbase_1 math_cbase_j math_czero " + "math_deg_to_rad math_e math_log10_of_e math_log2_of_e math_log_of_10 math_log_of_2 " + "math_pi math_pi_over_2 math_pi_over_3 math_pi_over_4 math_rad_to_deg math_sqrt_2 math_sqrt_pi mode_error monday " + "name_error nan neg_denormal neg_inf neg_normal neg_zero note open_ok output pos_denormal pos_inf pos_normal pos_zero " + "quiet_nan read_mode read_write_mode resolved right right_index round_inf round_nearest round_neginf round_zero " + "saturday state_closed state_open status_access_denied status_error status_item_exists " + "status_no_directory status_no_file status_not_empty status_not_found status_ok sunday " + "thursday true tuesday warning wednesday write_mode", + NULL, }; + + EDITLEXER lexVHDL = { SCLEX_VHDL, "vhdl", IDS_LEX_VHDL, L"VHDL", L"vhdl; vhd", L"", &KeyWords_VHDL, { { {STYLE_DEFAULT}, IDS_LEX_STR_63126, L"Default", L"", L"" }, //{ {SCE_VHDL_DEFAULT}, IDS_LEX_STR_63126, L"Default", L"", L"" }, - { {MULTI_STYLE(SCE_VHDL_COMMENTLINEBANG, SCE_VHDL_COMMENT, SCE_VHDL_BLOCK_COMMENT, 0)}, IDS_LEX_STR_63127, L"Comment", L"fore:#008800", L"" }, + { {MULTI_STYLE(SCE_VHDL_COMMENT, SCE_VHDL_COMMENTLINEBANG, SCE_VHDL_BLOCK_COMMENT, 0)}, IDS_LEX_STR_63127, L"Comment", L"fore:#008800", L"" }, { {SCE_VHDL_NUMBER}, IDS_LEX_STR_63130, L"Number", L"fore:#FF0000", L"" }, { {MULTI_STYLE(SCE_VHDL_STRING, SCE_VHDL_STRINGEOL, 0, 0)}, IDS_LEX_STR_63131, L"String", L"fore:#008000", L"" }, { {SCE_VHDL_OPERATOR}, IDS_LEX_STR_63132, L"Operator", L"fore:#B000B0", L"" }, { {SCE_VHDL_IDENTIFIER}, IDS_LEX_STR_63129, L"Identifier", L"", L"" }, - { {SCE_VHDL_KEYWORD}, IDS_LEX_STR_63128, L"Keyword", L"bold; fore:#0A246A", L"" }, + { {SCE_VHDL_KEYWORD}, IDS_LEX_STR_63128, L"Keyword", L"bold; fore:#0000FF", L"" }, { {SCE_VHDL_STDOPERATOR}, IDS_LEX_STR_63336, L"Standard Operator", L"bold; fore:#0A246A", L"" }, { {SCE_VHDL_ATTRIBUTE}, IDS_LEX_STR_63337, L"Attribute", L"", L"" }, { {SCE_VHDL_STDFUNCTION}, IDS_LEX_STR_63338, L"Standard Function", L"", L"" }, { {SCE_VHDL_STDPACKAGE}, IDS_LEX_STR_63339, L"Standard Package", L"", L"" }, { {SCE_VHDL_STDTYPE}, IDS_LEX_STR_63340, L"Standard Type", L"fore:#FF8000", L"" }, + { {SCE_VHDL_USERWORD}, IDS_LEX_STR_63274, L"Constant", L"fore:#A400A4", L"" }, EDITLEXER_SENTINEL } }; diff --git a/test/test_files/StyleLexers/styleLexVHDL/Sample_VHDL.vhdl b/test/test_files/StyleLexers/styleLexVHDL/Sample_VHDL.vhdl index d2734959a..76155b965 100644 --- a/test/test_files/StyleLexers/styleLexVHDL/Sample_VHDL.vhdl +++ b/test/test_files/StyleLexers/styleLexVHDL/Sample_VHDL.vhdl @@ -1 +1,243 @@ -The purpose of this dummy file is to create this directory. \ No newline at end of file +-- Simple Microprocessor Design (ESD Book Chapter 3) +-- Copyright 2001 Weijun Zhang +-- +-- DATAPATH composed of Multiplexor, Register File and ALU +-- VHDL structural modeling +-- datapath.vhd +---------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity datapath is +port( clock_dp: in std_logic; + rst_dp: in std_logic; + imm_data: in std_logic_vector(15 downto 0); + mem_data: in std_logic_vector(15 downto 0); + RFs_dp: in std_logic_vector(1 downto 0); + RFwa_dp: in std_logic_vector(3 downto 0); + RFr1a_dp: in std_logic_vector(3 downto 0); + RFr2a_dp: in std_logic_vector(3 downto 0); + RFwe_dp: in std_logic; + RFr1e_dp: in std_logic; + RFr2e_dp: in std_logic; + jp_en: in std_logic; + ALUs_dp: in std_logic_vector(1 downto 0); + oe_dp: in std_logic; + ALUz_dp: out std_logic; + RF1out_dp: out std_logic_vector(15 downto 0); + ALUout_dp: out std_logic_vector(15 downto 0); + bufout_dp: out std_logic_vector(15 downto 0) +); +end datapath; + +architecture struct of datapath is + +component smallmux is +port( I0: in std_logic_vector(15 downto 0); + I1: in std_logic_vector(15 downto 0); + I2: in std_logic_vector(15 downto 0); + Sel: in std_logic_vector(1 downto 0); + O: out std_logic_vector(15 downto 0) +); +end component; + +component reg_file is +port ( clock : in std_logic; + rst : in std_logic; + RFwe : in std_logic; + RFr1e : in std_logic; + RFr2e : in std_logic; + RFwa : in std_logic_vector(3 downto 0); + RFr1a : in std_logic_vector(3 downto 0); + RFr2a : in std_logic_vector(3 downto 0); + RFw : in std_logic_vector(15 downto 0); + RFr1 : out std_logic_vector(15 downto 0); + RFr2 : out std_logic_vector(15 downto 0) +); +end component; + +component alu is +port ( num_A: in std_logic_vector(15 downto 0); + num_B: in std_logic_vector(15 downto 0); + jpsign: in std_logic; + ALUs: in std_logic_vector(1 downto 0); + ALUz: out std_logic; + ALUout: out std_logic_vector(15 downto 0) +); +end component; + +component obuf is +port( O_en: in std_logic; + obuf_in: in std_logic_vector(15 downto 0); + obuf_out: out std_logic_vector(15 downto 0) +); +end component; + +signal mux2rf, rf2alu1: std_logic_vector(15 downto 0); +signal rf2alu2, alu2memmux: std_logic_vector(15 downto 0); + +begin + + U1: smallmux port map(alu2memmux, mem_data, + imm_data, RFs_dp, mux2rf); + U2: reg_file port map(clock_dp, rst_dp, RFwe_dp, + RFr1e_dp, RFr2e_dp, + RFwa_dp, RFr1a_dp, RFr2a_dp, + mux2rf, rf2alu1, rf2alu2 ); + U3: alu port map( rf2alu1, rf2alu2, jp_en, ALUs_dp, + ALUz_dp, alu2memmux); + U4: obuf port map(oe_dp, mem_data, bufout_dp); + + ALUout_dp <= alu2memmux; + RF1out_dp <= rf2alu1; + +end struct; + + + +-------------------------------------------------------- +-- Simple Microprocessor Design +-- +-- memory 256*16 +-- 8 bit address; 16 bit data +-- memory.vhd +-------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use work.constant_lib.all; + +entity memory is +port ( clock : in std_logic; + rst : in std_logic; + Mre : in std_logic; + Mwe : in std_logic; + address : in std_logic_vector(7 downto 0); + data_in : in std_logic_vector(15 downto 0); + data_out: out std_logic_vector(15 downto 0) +); +end memory; + +architecture behv of memory is + + type ram_type is array (0 to 255) of + std_logic_vector(15 downto 0); + signal tmp_ram: ram_type; + +begin + + + + write: process(clock, rst, Mre, address, data_in) + begin + if rst='1' then + tmp_ram <= (------------------------------------------------------------ + -- following instruction for debugging purpose + -- 0 => "0011001000101011", -- R2 <= #2B + -- 1 => "0011001100001001", -- R3 <= #09 + -- 2 => "0001001100001010", -- M[A] <= R3 + -- 3 => "0000011000001000", -- R6 <= M[8] + -- 4 => "0010001100100000", -- M[R3] <= R2 + -- 5 => "0100001100100000", -- R3 <= R3 + R2 + -- 6 => "0101001001100000", -- R2 <= R2 - R6 + -- 7 => "0110000000000000", -- jz if R0=0 + -- 8 => "1111000000000000", -- halt + ------------------------------------------------------------- + + -- program to generate 10 fabonacci number + + 0 => "0011000000000000", -- mov R0, #0 + 1 => "0011000100000001", -- mov R1, #1 + 2 => "0011001000110100", -- mov R2, #52 + 3 => "0011001100000001", -- mov R3, #1 + 4 => "0001000000110010", -- mov M[50], R0 + 5 => "0001000100110011", -- mov M[51], R1 + 6 => "0001000101100100", -- mov M[100], R1 + 7 => "0100000100000000", -- add R1, R0 + 8 => "0000000001100100", -- mov M[100], R0 + 9 => "0010001000010000", -- mov M[R2], R1 + 10 => "0100001000110000", -- add R2, R3 + 11 => "0000010000111011", -- mov R4, M[59] + 12 => "0110010000000101", -- jz R4, #6 + + 13 => "0111000000110010", -- output M[50] + 14 => "0111000000110011", -- ,, M[51] + 15 => "0111000000110100", -- ,, M[52] + 16 => "0111000000110101", -- ,, M[53] + 17 => "0111000000110110", -- ,, M[54] + 18 => "0111000000110111", -- ,, M[55] + 19 => "0111000000111000", -- ,, M[56] + 20 => "0111000000111001", -- ,, M[57] + 21 => "0111000000111010", -- ,, M[58] + 22 => "0111000000111011", -- ,, M[59] + + 23 => "1111000000000000", -- halt + others => "0000000000000000"); + else + if (clock'event and clock = '1') then + if (Mwe ='1' and Mre = '0') then + tmp_ram(conv_integer(address)) <= data_in; + end if; + end if; + end if; + end process; + + read: process(clock, rst, Mwe, address) + begin + if rst='1' then + data_out <= ZERO; + else + if (clock'event and clock = '1') then + if (Mre ='1' and Mwe ='0') then + data_out <= tmp_ram(conv_integer(address)); + end if; + end if; + end if; + end process; +end behv; + + +-------------------------------------------------------- +-- Simple Microprocessor Design (ESD Book Chapter 3) +-- Copyright 2001 Weijun Zhang +-- +-- big multiplexor of control unit has +-- four 16-bit inputs and one 16-bit output +-- bigmux.vhd +-------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity bigmux is +port( Ia: in std_logic_vector(15 downto 0); + Ib: in std_logic_vector(15 downto 0); + Ic: in std_logic_vector(15 downto 0); + Id: in std_logic_vector(15 downto 0); + Option: in std_logic_vector(1 downto 0); + Muxout: out std_logic_vector(15 downto 0) +); +end bigmux; + +architecture behv of bigmux is + +begin + + process(Ia, Ib, Ic, Id, Option) + begin + case Option is + when "00" => Muxout <= Ia; + when "01" => Muxout <= Ib; + when "10" => Muxout <= Ic; + when "11" => Muxout <= Id; + when others => + end case; + end process; + +end behv; +